Error analysis of FFT architectures for digital video applications

Author

Hui, Colin C W ; Ding, Tiong Jiu ; McCanny, John V. ; Woods, Roger F.

Author_Institution

Inst. of Adv. Microelectron., Queen´´s Univ., Belfast, UK

Volume

2

fYear

1996

fDate

13-16 Oct 1996

Firstpage

820

Abstract

Describes how worst-case error analysis can be applied to solve some of the practical issues in the development and implementation of a low power, high performance radix-4 FFT chip for digital video applications. The chip has been fabricated using a 0.6 μm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm² and dissipates IW, leading to a cost-effective silicon solution for high quality video processing applications. The analysis focuses on the effect that different radix-4 architectural configurations and finite wordlengths has on the FFT output dynamic range. These issues are addressed using both mathematical error models and through extensive simulation

Keywords

CMOS digital integrated circuits; digital signal processing chips; fast Fourier transforms; real-time systems; video signal processing; 0.6 micron; 1 W; CMOS technology; FFT architectures; complex forward FFT; die area; digital video applications; finite wordlengths; inverse FFT; mathematical error models; radix-4 FFT chip; real-time video; video processing applications; worst-case error analysis; Buildings; CMOS technology; Dynamic range; Error analysis; Fixed-point arithmetic; Frequency domain analysis; Mathematical model; Microelectronics; Motion compensation; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on

Conference_Location

Rodos

Print_ISBN

0-7803-3650-X

Type

conf

DOI

10.1109/ICECS.1996.584488

Filename

584488