An efficient digital FIR filter design for 64 QAM

Digital FIR filters show an efficient performance/area ratio only when operating at input/output rates of less than 6 M samples/sec with limited accuracy and limited number of stages (taps). This work presents FIR computation techniques that lead to efficient implementations with respect to area, accuracy and speed of calculations. These techniques utilise parallelism and pipelining both in word and bit level to achieve high speed, expandability with respect to the number of stages and low cost solutions for incrementing accuracy. Further, it presents realisations of these implementation techniques using FPGAs. These can be placed between the mapper and the sin/cos-generator in a 64-QAM modulator working at rates of 240 Mbits/sec