Compact NEMS FPGA design for harsh environment and low power requirement

We present implementation of field-programmable gate array (FPGA) using new NEMS devices that can be configured to implement any 2-input basic logic gates using a single structure [3]. This enables the implementation of 2 mechanical delays for 4-input compact Configurable Logic Block (CLB). These NEMS CLBs use only nine NEMS, instead of 150 switches used in CMOS, and provide a programmable interconnect that minimize power. NEMS devices are generally larger, slower, and less reliable than their CMOS counter parts. Our approach of realizing a logic gate within a single device structure reduces the number of switches needed to implement logic gates improving reliability, reducing the real estate and delay. In FPGA´s the programming is usually done once and the resulting functionality constitute the desired outcome. Thus, the NEMS mechanical delay is minimized and given the reduced leakage power of NEMS, it presents a considerable advantage over CMOS.