Design and Real Time Implementation of a Novel Combined CA-CFAR/SLB System on TMS320C67x Processor

In this paper, we present a novel approach for real time implementation of a combined Cell Averaging-Constant False Alarm Rate (CA-CFAR) detector and SideLobe Blanking (SLB) system. The proposed approach has been implemented using the Texas Instruments TMS320C6711 Digital Signal Processor (DSP). We propose also an optimized procedure for CFAR based threshold estimation using a Generalized Automatic Sliding Window technique (GASW) which efficiently uses data to reduce the memory access number and exploits pre-computed values to set the new threshold for adjacent cell. DSP implementation results are presented and discussed.