Several new concepts to bridge the "Logic Effort" research and SoC timing closure practice

Author

Xiu, Liming

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

2005

fDate

10 Oct. 2005

Firstpage

229

Lastpage

235

Abstract

"Logic Effort" is academic research in the field of circuit optimization. The aim of this research is to achieve the fastest circuit implementation of a logic function by using the least amount of silicon resource. The fruit of this "Logic Effort" research has been utilized by Magma in real world timing closure practice and has resulted in significant success. However, the "gain" concept used by Magma in its practice is not user-friendly and has caused lot of confusions. This paper introduces several new concepts which can function as a bridge between the "Logic Effort" circuit optimization technique and real world timing closure practice.

Keywords

circuit optimisation; logic design; system-on-chip; timing; Logic Effort research; SoC timing closure; circuit optimization; logic synthesis; system on chip; Bridge circuits; Circuit optimization; Circuit synthesis; Delay; Geometry; Logic circuits; Silicon; System-on-a-chip; Timing; Very large scale integration; Logic Effort; System on Chip; logic synthesis; physical synthesis; timing closure;

fLanguage

English

Publisher

ieee

Conference_Titel

Architecture, Circuits and Implementtation of SOCs, 2005. DCAS '05. Proceedings of the 2005 IEEE Dallas/CAS Workshop:

Print_ISBN

0-7803-9515-8

Type

conf

DOI

10.1109/DCAS.2005.1611177

Filename

1611177