Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance

Microprocessor clock frequency (FCLK) is traditionally determined based on maximum supply voltage (Vcc) droop and temperature specifications. Since typical usage patterns usually run at nominal Vcc and temperature, these infrequent dynamic variations severely limit FCLK. The concept of timing-error detection and correction in previous work by Ernst, D., et al, (2003) is extended and implemented in a test-chip in 65nm CMOS in Bai, P., et al, (2004) to explore the effectiveness of resilient circuits in eliminating Vcc and temperature FCLK guardbands as well as exploiting path-activation probabilities to maximize throughput (TP).