DocumentCode
346568
Title
A compact model for depletion MOSFETs in smart power applications including source and drain resistance
Author
Gohler, L. ; Kelting, K.
Author_Institution
Univ. der Bundeswehr Munchen, Neubiberg, Germany
Volume
2
fYear
1999
fDate
1999
Firstpage
1080
Abstract
This paper presents a compact depletion MOSFET model applicable in smart power circuit simulations. For the first time, a complete description of all internal states and the stored charge in both on-state and subthreshold region of a DMOSFET including source and drain resistance is derived. The equation set consists of explicit expressions and requires 25 parameters only
Keywords
MOS integrated circuits; circuit simulation; electric resistance; power MOSFET; power integrated circuits; semiconductor device models; DMOSFET; compact depletion MOSFET model; depletion MOSFET; drain resistance; internal states; on-state region; smart power applications; smart power circuit simulations; source resistance; stored charge; subthreshold region; CMOS technology; Circuit simulation; Energy consumption; Equations; FETs; Low voltage; MOS devices; MOSFETs; Power system modeling; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Industry Applications Conference, 1999. Thirty-Fourth IAS Annual Meeting. Conference Record of the 1999 IEEE
Conference_Location
Phoenix, AZ
ISSN
0197-2618
Print_ISBN
0-7803-5589-X
Type
conf
DOI
10.1109/IAS.1999.801638
Filename
801638
Link To Document