Electrical performance analysis of a three-dimensional package

Three-dimensional packaging is considered to offer a solution for high packaging density and enhanced electrical performance, which are required for the present and future electronic systems. A new type of three-dimensional package was recently developed. These were named “memory cubes”, in which thin small outline J-leaded packages or thin quad flat J-leaded packages were stacked, and electrically interconnected by soldering of the outer leads. Analyses of electrical performances of the memory cubes as the main memories in a computer system were made through the electrical simulations of a 4 Mb×9 DRAM memory cube and an equivalent 4 Mb×9 DRAM single inline memory module. Electrical simulation showed that memory cube reduced the capacitance load of the longest on-board nets of typical memory board by 5% to 10%, reduced the reflection behavior of these nets by its lumped load character, and resulted in an overall driver-to-receiver net performance improvement versus the equivalent single inline memory module by about 15%