Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies

Author

Wambacq, Piet ; Mercha, A. ; Scheir, K. ; Verbruggen, B. ; Borremans, J. ; De Heyn, V. ; Thijs, S. ; Linten, D. ; Van der Plas, G. ; Parvais, B. ; Dehan, M. ; Decoutere, S. ; Soens, C. ; Collaert, N. ; Jurczak, M.

Author_Institution

IMEC, Heverlee

fYear

2008

fDate

3-7 Feb. 2008

Firstpage

528

Lastpage

633

Abstract

CMOS scaling beyond 45nm requires devices that deviate from the planar bulk transistor with a polysilicon gate and nitrided silicon dioxide (SiON) as gate dielectric. To downscale planar bulk devices, strain is used to boost mobility and new materials are introduced in the gate stack. Multigate devices such as fully-depleted SOI FinFETs (Fig. 29.4.1) are also candidates for downscaling beyond 45nm.

Keywords

CMOS integrated circuits; MOSFET; analogue integrated circuits; silicon-on-insulator; CMOS scaling; CMOS technology; FinFET; SOI; analog-circuit benchmarking; gate dielectric; planar bulk transistor; silicon-on-insulator; size 45 nm; CMOS analog integrated circuits; CMOS technology; Energy consumption; FinFETs; Frequency measurement; Gain measurement; Noise measurement; Power measurement; Radio frequency; Tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International

Conference_Location

San Francisco, CA

Print_ISBN

978-1-4244-2010-0

Electronic_ISBN

978-1-4244-2011-7

Type

conf

DOI

10.1109/ISSCC.2008.4523290

Filename

4523290