Processor design considerations for wireless sensor network

Wireless sensor networks are task-based networks, which have become one of the hottest research and application areas and already enabled numerous embedded wireless applications such as military, environmental monitoring, intelligent building etc. Low power design is an important topic of wireless sensor network. In this paper, a low-power processor (WO-LPP) is presented for WSN. Our processor has 8-bit simple 3-stage pipeline even-driven RISC ISA core with on-chip program flash and internal SRAM. At the same time, on-chip even-based task management, on-chip hardware management and power management scheme are coordinately designed with some general peripheral devices to meet most application environments. An AES (advanced encryption standard) engine is also designed. Application results show the processor is specially optimized for wireless sensor network.