A voltage level converter circuit design with low power consumption

A conventional level converter, named the dual cascode voltage switch (DCVS), interposed between gates operating on different supply voltages in a CMOS logic circuit, to prevent the short-circuit current and reduce power consumption. Although the level converter blocks the short-circuit current, it consumes relatively large dynamic power when it carries out a switching operation. If the CMOS logic circuit must have many level converters, the power consumption thereof will increase to nullify the effort of decreasing power consumption by using the two supply voltages VDDL and VDDH. Furthermore, this conventional level converter has relatively large delay because it is rely on a contention between different transistors on the level conversion path (Kuroda et al., 1996). Hence, we proposed an improved circuit to reduce the contention problem so as to achieve high speed and low power consumption. Next, operation of the proposed level converter circuit is explained