A 3.3-V, 1.9-GHz, high linear CMOS up-mixer with multi-tanh linearization technique

Author

Xi, Zhanguo ; Qin, Yajie ; Hong, Zhiliang

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai

Volume

1

fYear

2005

fDate

24-0 Oct. 2005

Firstpage

355

Lastpage

358

Abstract

This paper presents a single side band up-mixer implemented in SMIC 0.35 mum CMOS technology. It can be used in low-IF direct conversion PCS 1900 (1850-1910MHz) transceiver systems. The mixer is based on multi-tanh linearization technique and achieves high linearity. It operates at a single power supply of 3.3V and consumes only 6mA. The up-mixer with the output buffer achieves an IIP3 of 8dBm and a 1-dB compression point of 0dBm

Keywords

CMOS analogue integrated circuits; linearisation techniques; mixers (circuits); radiofrequency integrated circuits; transceivers; 0.35 micron; 1.9 GHz; 1850 to 1910 MHz; 3.3 V; 6 mA; PCS 1900 transceiver systems; SMIC CMOS technology; high linearity CMOS up-mixer; low-IF direct conversion; multi-tanh linearization technique; single side band up-mixer; Baseband; CMOS technology; Linearity; Linearization techniques; Personal communication networks; Power supplies; Radio transmitters; Transceivers; Transconductance; Voltage; CMOS; Mixer; RFIC; high linearity; multi-tanh; up-converter;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Conference_Location

Shanghai

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611336

Filename

1611336