A 10-bit 30-MS/s 50mW pipelined A/D converter

Author

Xi, Chen ; Lenian, He ; Xiaolang, Yan

Author_Institution

Inst. of VLSI Design, Zhejiang Univ., Hangzhou

Volume

1

fYear

2005

fDate

24-0 Oct. 2005

Firstpage

378

Lastpage

382

Abstract

A 10-bit 30-Msample/s pipelined analog-to-digital converter is designed and implemented in a 0.6mum CMOS technology. Sampling capacitors scaling technique is employed to reduce the power dissipation. The digital correction technique is used to relax the offset requirement of the comparators. A sample-and-hold amplifier (SHA) is also used to improve the signal-to-noise and distortion ratio (SNDR) performance and the linearity of ADC. The simulation and experiment results reveal that the ADC designed with this method achieves the SNDR of 58dB or the ENOB of 9.34 at full speed of 30MHz when input frequency is 7MHz. Furthermore, the ADC consumes only 50mW power at 5V supply voltage with a low power operational transconductance amplifier (OTA) and the dynamic comparators

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); integrated circuit design; operational amplifiers; sample and hold circuits; 0.6 micron; 10 bit; 30 MHz; 5 V; 50 mW; 7 MHz; CMOS technology; digital correction technique; dynamic comparators; operational transconductance amplifier; pipelined A-D converter; sample-and-hold amplifier; sampling capacitor scaling technique; Analog-digital conversion; CMOS technology; Capacitors; Design methodology; Distortion; Frequency; Linearity; Power dissipation; Power supplies; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Conference_Location

Shanghai

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611342

Filename

1611342