High level modeling of a ΣΔ modulator for the test of a SNDR BIST

The test of analogue and mixed-signal (AMS) cores requires the use of expensive AMS testers and accessibility to internal analogue nodes. The test cost can be considerably reduced by the use of built-in-self-test (BIST) techniques. One of these techniques consists in generating analogue test signals from digital test patterns (obtained via SigmaDelta modulation) and converting the responses of the analogue modules into digital signatures that are compared with the expected ones. In this paper, we tried to test the efficiency of this technique by associating to the BIST a high level VHDL-AMS description of a SigmaDelta modulator. This work details our modeling strategy to obtain a fast and accurate virtual prototype of the modulator.