A New Structure for Capacitor-Mismatch-Insensitive Multiply-By-Two Amplification

Author

Zare-Hoseini, Hashem ; Shoaei, Omid ; Kale, Izzet

Author_Institution

Applied DSP and VLSI Research Group, Department of Electronic Systems, University of Westminster, London. Email: h.zhoseini@wmin.ac.uk

Volume

1

fYear

2005

fDate

24-27 Oct. 2005

Firstpage

499

Lastpage

503

Abstract

A new approach to achieve a Switched-Capacitor (SC) Multiply-By-Two (MBT) Gain-Stage (GS) with reduced sensitivity to capacitors´ mismatches is presented in this paper. It is based on sampling fully differential input signals onto both plates of the input capacitors rather than sampling onto one plate of the capacitors with the other tied to a reference. It uses one operational amplifier (op-amp) in two phases to produce the gain of two (x2). Comparing to the conventional multiply-by-two gain-stage, the mismatches between the capacitors has a very smaller influence on the accuracy of the gain of two (x2). Analytical and circuit-level analysis of the architecture and the conventional structure are presented using a generic 0.35μm CMOS technology.

Keywords

CMOS technology; Capacitors; Circuit analysis; Digital signal processing; Energy consumption; Operational amplifiers; Sampling methods; Transfer functions; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2005. ASICON 2005. 6th International Conference On

Print_ISBN

0-7803-9210-8

Type

conf

DOI

10.1109/ICASIC.2005.1611360

Filename

1611360