DocumentCode
3468623
Title
Topology-driven cell layout migration with collinear constraints
Author
De-Shiun Fu ; Ying-Zhih Chaung ; Yen-Hung Lin ; Yih-Lang Li
Author_Institution
Comput. Sci. Dept., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2009
fDate
4-7 Oct. 2009
Firstpage
439
Lastpage
444
Abstract
Traditional layout migration focuses on area minimization, thus suffered wire distortion, which caused loss of layout topology. A migrated layout inheriting original topology owns original design intention and predictable property, such as wire length which determines the path delay importantly. This work presents a new rectangular topological layout to preserve layout topology and combine its flexibility of handling wires with traditional scan-line based compaction algorithm for area minimization. The proposed migration flow contains devices and wires extraction, topological layout construction, unidirectional compression combining scan-line algorithm with collinear equation solver, and wire restoration. Experimental results show that cell topology is well preserved, and a several times runtime speedup is achieved as compared with recent migration research based on ILP (integer linear programming) formulation.
Keywords
circuit layout; integer programming; linear programming; minimisation; network topology; wires (electric); ILP; area minimization; cell topology; collinear equation solver; integer linear programming; path delay; scan line based compaction algorithm; topological layout construction; topology driven cell layout migration; wire distortion; wire restoration; wires extraction; Algorithm design and analysis; Compaction; Delay; Foundries; Integer linear programming; Runtime; Semiconductor device manufacture; Shape; Topology; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design, 2009. ICCD 2009. IEEE International Conference on
Conference_Location
Lake Tahoe, CA
ISSN
1063-6404
Print_ISBN
978-1-4244-5029-9
Type
conf
DOI
10.1109/ICCD.2009.5413118
Filename
5413118
Link To Document