Congestion and performance driven full-chip scalable routing framework

Timing is one of the emerging issues in deep sub-micrometer technology which has great influence on the circuit performance. This paper presents a novel full-chip scalable routing framework, which considers the routing congestion and the circuit performance simultaneously. The framework features the fast pattern and framed shortest path global router and a maze-based congestion-driven detailed router. We also introduce a criticality-driven least flexibility prior net ordering technique which assigns timing-critical nets higher priority for performance concern. Then nets are routed one by one according to their priorities and the routing resource is updated immediately after each routing, which results in very accurate resource estimation. We have tested our routing framework on a set of commonly used benchmark circuits and compared the results with a previous multilevel routing framework. The experimental results are very promising