A 4-level storage 4 Gb DRAM

Bit-cost reduction is one of the most serious issues for file application DRAMs. Chip size reduction or density increase has been an effective solution. Lithographic technology has permitted this density increase through 70% reduction in the minimum design rule for each subsequent DRAM generation. However, for further density increase, another memory cell reduction technology is needed. Multi-level storage is one circuit technology that can reduce the effective cell size since it allows the storage of multiple voltage levels in a single memory cell functioning as a multi-bit memory. When four levels are stored in a single memory cell, the effective cell size is halved. The authors show that a charge-coupling sense amplifier, charge-sharing restore, and time-shared sensing increase speed and reduce sense-circuit area for 4 Gb DRAM.