Novel on-chip communication data channel architecture used in USB 2.0

This paper proposes a novel data channel architecture for on chip communication used in USB 2.0 device controller, which is integrated to SoC. Through dynamic allocating and reclaiming limited channel buffer resource on runtime, channel throughput was greatly improved without increasing RAM size. This novel channel architecture was applied to home network SoC platform successfully, testing result shows that the throughput of this new architecture is improved by 63% compared to existing channel architecture, and the usage ratio of buffer resource achieved 95% in average