Single-chip 4-channel 155 Mb/s CMOS LSI chip for ATM SONET/SDH framing and clock/data recovery

To introduce asynchronous transfer mode (ATM) to mass applications, it is desirable to reduce cost and board area of ATM switches while maintaining high data speed and good jitter quality. A 4-port CMOS single chip LSI quad physical layer controller (QPLC) for 155.62 Mb/s (STS-3c) meets these requirements by integrating four receive/transmit ports, each of which has a clock recovery PLL and SONET/SDH framing functions. The clock recovery PLL uses a current-regulated constant-amplitude differential VCO for low jitter. The bit-rate at each port can be separately changed to 51.84 Mb/s (STS-1) or 25.92 Mb/s (STS-1R).