Fast Settling and Low Phase Noise Synthesizer and VCO Design

This paper describes a new design approach to reduce settling time without significantly enlarging PLL bandwidth, hence, getting a better phase noise performance. The PLL settling time is a function of loop bandwidth, jumping frequency and frequency tolerance. The jumping frequency from initial state to the final settling state can be minimized by VCO calibration before PLL start. Frequency locked loop (FLL) as VCO calibration can set the VCO frequency near by the final frequency within a short time. The PLL can settle quickly without widening the loop bandwidth. Combining the FLL, PLL, and VCO design techniques can reduce locking time without sacrificing phase noise performance. The new design scheme can relax the fundamental trade-off between PLL bandwidth and settling time