A 600 MHz superscalar RISC microprocessor with out-of-order execution

Author

Gieseke, B.A. ; Allmon, R.L. ; Bailey, D.W. ; Benschneider, B.J. ; Britton, S.M. ; Clouser, J.D. ; Fair, H.R., III ; Farrell, J.A. ; Gowan, M.K. ; Houghton, C.L. ; Keller, J.B. ; Lee, T.H. ; Leibholz, D.L. ; Lowell, S.C. ; Matson, M.D. ; Matthew, R.J. ; P

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

fYear

1997

fDate

8-8 Feb. 1997

Firstpage

176

Lastpage

177

Abstract

A six-issue, four-fetch, out-of-order execution, 6OOMHz Alpha microprocessor achieves an estimated 40SpecInt95, 60SpecFP95 and 1800MB/s on McCalpin Stream. The 16.7x18.8mm2 die contains 15.2M transistors and dissipates an estimated 72W. It is in 2.0V, 6-metal, 0.35/spl mu/m CMOS with CMP planarization. The chip is in a 587-pin ceramic IPGA with 198 pins for VDD/VSS that includes a CuW heat slug for low thermal resistance between die and detachable heat sink. An on-chip PLL performs frequency multiplication of a differential PECL reference and synchronizes I/O by phase-aligning a CPU clock to the reference.

Keywords

CMOS digital integrated circuits; integrated circuit packaging; microprocessor chips; reduced instruction set computing; 0.35 micron; 1800 MB/s; 2.0 V; 600 MHz; 72 W; CMOS; CMP planarization; CPU clock phase-alignment; McCalpin Stream; ceramic IPGA; detachable heat sink; differential PECL reference; frequency multiplication; out-of-order execution; superscalar RISC microprocessor; thermal resistance; Ceramics; Heat sinks; Microprocessors; Out of order; Pins; Planarization; Reduced instruction set computing; Resistance heating; Thermal resistance; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3721-2

Type

conf

DOI

10.1109/ISSCC.1997.585323

Filename

585323