A two-path bandpass /spl Sigma//spl Delta/ modulator for digital IF extraction at 20 MHz

There is expanding interest in the possibility of moving the intermediate frequency (IF) signal processing in radio receivers and radio test equipment from the analog domain into the digital domain. Digitization of IF processing confers several important advantages, including greater reliability, potentially lower power consumption, and improved performance as technology scales. Unfortunately, as analog signal processing is eliminated and the A/D conversion is moved away from baseband, the signal that must be digitized has a larger dynamic range, and the converter must operate at a higher sampling rate. This work introduces a two-path, switched-capacitor architecture for a bandpass /spl Sigma//spl Delta/ modulator that is suited to digitizing narrowband radio signals with large dynamic range. A fourth-order bandpass modulator is implemented in a standard 0.6 /spl mu/m, single-poly, triple-metal CMOS process. Operating from a single 3.3 V supply, the modulator digitizes a 200 kHz signal centered at an IF of 20 MHz with an extrapolated dynamic range of 75 dB.