• DocumentCode
    3471078
  • Title

    Utilization of the power losses map in the design of DC/DC converters

  • Author

    Barrado, A. ; Pleite, J. ; Lazaro, A. ; Vazquez, R. ; Olias, E.

  • Author_Institution
    Escuela Politecnica Superior, Univ. Carlos III, Madrid, Spain
  • Volume
    2
  • fYear
    1998
  • fDate
    17-22 May 1998
  • Firstpage
    1543
  • Abstract
    In this paper, the authors propose a power losses map in order to optimize the design of DC/DC power converters. The power losses map is a level curves graph which shows, in advance, the theoretical power losses at the different operation-points where it is possible to design a DC/DC power converter, under the same specifications. They present the use of the power losses map especially when there are some restrictions in the design, such as the converter size, the magnetic core size, the maximum drain-source voltage, the conduction mode, when some component is imposed, etc. Finally, a comparison between both the theoretical power losses map and experimental results from flyback power converters is also presented
  • Keywords
    DC-DC power convertors; circuit optimisation; losses; power MOSFET; power semiconductor switches; switching circuits; DC/DC power converters; conduction mode; design optimisation; design restrictions; drain-source voltage; level curves graph; magnetic core size; operation-points; power converter size; power losses map; specifications; Costs; DC-DC power converters; Design optimization; Guidelines; Inductance; Magnetic cores; Magnetic separation; Switched-mode power supply; Topology; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Electronics Specialists Conference, 1998. PESC 98 Record. 29th Annual IEEE
  • Conference_Location
    Fukuoka
  • ISSN
    0275-9306
  • Print_ISBN
    0-7803-4489-8
  • Type

    conf

  • DOI
    10.1109/PESC.1998.703381
  • Filename
    703381