• DocumentCode
    3471139
  • Title

    Parallel processing RAM chip with 256 Mb DRAM and quad processors

  • Author

    Murakami, K. ; Shirakawa, S. ; Miyajima, H.

  • Author_Institution
    Kyushu Univ., Fukuoka, Japan
  • fYear
    1997
  • fDate
    8-8 Feb. 1997
  • Firstpage
    228
  • Lastpage
    229
  • Abstract
    Parallel processing RAM (PPRAM) is an architectural framework for merged memory/logic application-specific standard products (ASSPs). It integrates onto a single chip (1) a large amount of DRAM and/or SRAM and/or flash EEPROM and/or FRAM (2) zero or more general-purpose processors and/or application-specific processors and/or FPGA, etc.; (3) a network interface based on a common communication protocol. Many different implementations of PPRAM are possible. All provide a common network interface (called PPRAM-link). System designers will be able to construct computer systems of any size, of any functionality, and of any performance, just by choosing the required PPRAM chips from those various PPRAM implementations and by interconnecting them through the PPRAM-link network.
  • Keywords
    DRAM chips; field programmable gate arrays; memory architecture; protocols; 256 Mbit; DRAM; FPGA; PPRAM; PPRAM-link; architectural framework; common communication protocol; merged memory/logic application-specific standard products; network interface; parallel processing RAM chip; quad processors; Application specific processors; EPROM; Ferroelectric films; Field programmable gate arrays; Logic; Network interfaces; Nonvolatile memory; Parallel processing; Random access memory; Read-write memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-3721-2
  • Type

    conf

  • DOI
    10.1109/ISSCC.1997.585356
  • Filename
    585356