Design of a 128-point Fourier Transform Chip for UWB Applications

Author

Chen, Sheng ; Yu, Ying ; Chen, Binglai ; Lai, Songlin ; Zeng, Yibin ; Zhang, Yazhen ; Wang, Cunguang

Author_Institution

Dept. of Electron., Fuzhou Univ.

fYear

2006

fDate

2006

Firstpage

1957

Lastpage

1959

Abstract

This paper presents a novel 128-point FFT processor developed primarily for the application in a MB-OFDM based UWB system, in which a N=4*4*4*2 algorithm was exploited. A radix-2² unit and a radix-2²/2 unit form the two-stage pipelined architecture. The parallel butterfly unit enhances the processing speed efficiently. Moreover, a unique butterfly both shared by radix-2² and radix-2 is proposed to save the silicon area. The feedback loop in butterfly units is used to avoid storing the data into the RAM at every clock. The design was carried out in the SMIC 0.25-mum five-metal layer BiCMOS technology. Clock rate at 66MHz has been achieved

Keywords

BiCMOS integrated circuits; OFDM modulation; fast Fourier transforms; microprocessor chips; ultra wideband communication; 0.25 micron; 66 MHz; BiCMOS technology; FFT processor; Fourier transform chip; MB-OFDM; UWB system; feedback loop; parallel butterfly unit; silicon area; two-stage pipelined architecture; Algorithm design and analysis; BiCMOS integrated circuits; Clocks; Digital TV; Discrete Fourier transforms; Electrical products; Feedback loop; Fourier transforms; Silicon; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306540

Filename

4098592