An all digital phase-locked loop based on double edge triggered flip-flop

In this paper an all digital phase-locked loop (ADPLL) that is based on double edge triggered D-flip-flops (DETDFF) was proposed. By using DETDFF, the functions of bi-directional zero crossing sample and phase detection, which are key issues in the designing process of ADPLL with several new important characteristics, were implemented. In addition, the run speed of each part in the loop was enhanced to twice the conventional, while the clock frequency of the digital controlled oscillator (DCO) is half the past. An ADPLL system was designed by using very high speed integrated circuit hardware description language (VHDL) and implemented on a prototype based on a chip of VIRTEX FPGA VCU400BG432. And simulation and experimental results demonstrate that the proposed system is characteristic of its high lock speed, low power dissipation, simple system structure and easy system integration. It needs only few modifications in VHDL codes to be used in other systems, which remarkably reduces the difficult degree in ADPLL design and evidently shortens the time period of ADPLL system design. Specially, it can be used as IP (intellectual property) cores with applications to the design of system-on-chip (SOC)