DocumentCode
3473905
Title
On compliance test of on-chip bus for SOC
Author
Lin, Hue-Min ; Yen, Chia-Chih ; Shih, Che-Hua ; Jou, Jing-Yang
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
2004
fDate
27-30 Jan. 2004
Firstpage
328
Lastpage
333
Abstract
We employ a monitor-based approach for on-chip bus (OCB) compliance test. To describe the OCB protocols, we propose a FSM model, which can help to extract the necessary properties systematically and verify the data part of a bus transfer efficiently. To demonstrate our methodology, we illustrate two OCB protocols, WISHBONE and AMBA AHB, as the study cases. The experimental results show that we can verify the OCB protocols efficiently and detect the design errors when tests fail.
Keywords
finite state machines; formal verification; logic testing; protocols; system buses; system-on-chip; AMBA AHB protocol; WISHBONE protocol; compliance test; design error detection; monitor-based approach; on-chip bus; system-on chip; Automata; Buildings; Communication standards; Data mining; Logic design; Monitoring; Optical character recognition software; Protocols; System-on-a-chip; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN
0-7803-8175-0
Type
conf
DOI
10.1109/ASPDAC.2004.1337590
Filename
1337590
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