DocumentCode
3474592
Title
Design of a 1GHz Digital PLL Using 0.18mu m CMOS Technology
Author
Janardhan, H.
Author_Institution
Dept. of Electr. Eng., California State Univ., Long Beach, CA
fYear
2006
fDate
10-12 April 2006
Firstpage
599
Lastpage
600
Abstract
A digital phase-locked loop (DPLL) is designed and is shown to have 1GHz operation with lock time of 643.36ns. The lock time was reduced by adjusting the charge pump current and the loop filter capacitor. There was a trade-off between the lock time, loop filter capacitor, and ripples on the output of the VCO. Design procedures and simulation results are illustrated
Keywords
CMOS logic circuits; digital phase locked loops; logic design; 1 GHz; 643.36 ns; VCO; charge pump current; digital PLL; digital phase-locked loop; lock time; loop filter capacitor; micrometer CMOS technology; CMOS technology; Capacitors; Charge pumps; Clocks; Filters; Inverters; Phase detection; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Technology: New Generations, 2006. ITNG 2006. Third International Conference on
Conference_Location
Las Vegas, NV
Print_ISBN
0-7695-2497-4
Type
conf
DOI
10.1109/ITNG.2006.50
Filename
1611669
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