• DocumentCode
    3474611
  • Title

    Hierarchical random-walk algorithms for power grid analysis

  • Author

    Qian, Haifeng ; Sapatnekar, Sachin S.

  • Author_Institution
    Dept. of Electr & Comput. Eng.,, Minnesota Univ., Minneapolis, MN, USA
  • fYear
    2004
  • fDate
    27-30 Jan. 2004
  • Firstpage
    499
  • Lastpage
    504
  • Abstract
    We present a power grid analyzer that combines a divide-and-conquer strategy with a random-walk engine. A single-level hierarchical method is first described and then extended to multilevel and "virtual-layer" hierarchy. Experimental results show that these algorithms not only achieve speedups over the generic random-walk method, but also are more robust in solving various types of industrial circuits. For example, a 71K-node circuit is solved in 4.16 seconds, showing a more than 4 times speedup over the generic method; a 348K-node wire-bond power grid, for which the performance of the generic method degrades, is solved in 75.88 seconds.
  • Keywords
    VLSI; circuit complexity; divide and conquer methods; power integrated circuits; transient analysis; divide-and-conquer strategy; hierarchical random-walk algorithms; power grid analysis; random-walk engine; Algorithm design and analysis; Equations; Power grids; RLC circuits; Robustness; Signal design; Transient analysis; Vectors; Voltage; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
  • Print_ISBN
    0-7803-8175-0
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2004.1337626
  • Filename
    1337626