A Testing Approach for Xilinx FPGA´s CLB

There have been some researches of testing CLBs in SRAM-based FPGA in recently years. While no research in existing papers has focused on testing and locating multiple stuck-at faults in CLBs. We propose a testing approach for this multiple faults model and try to reduce the number of test configurations (TCs) and test vectors (TVs). It is certificated that in the proposed testing, the number of TCs for testing XC4000 is fixed to 8, and the number of TCs for locating is 8*(2+AC).