High performance pipelined FPGA implementation of the SHA-3 hash algorithm

Author

Ioannou, Lenos ; Michail, Harris E. ; Voyiatzis, Artemios G.

Author_Institution

Dept. of Electr. Eng., Cyprus Univ. of Technol., Lemesos, Cyprus

fYear

2015

fDate

14-18 June 2015

Firstpage

68

Lastpage

71

Abstract

The SHA-3 cryptographic hash algorithm is standardized in FIPS 202. We present a pipelined hardware architecture supporting all the four SHA-3 modes of operation and a high-performance implementation for FPGA devices that can support both multi-block and multi-message processing. Experimental results on different FPGA devices validate that the proposed design achieves significant throughput improvements compared to the available literature.

Keywords

cryptography; field programmable gate arrays; pipeline processing; FIPS 202; FPGA devices; SHA-3 cryptographic hash algorithm; SHA-3 modes; field programmable gate array; high performance pipelined FPGA implementation; multiblock processing; multimessage processing; pipelined hardware architecture; Algorithm design and analysis; Computer architecture; Cryptography; Field programmable gate arrays; NIST; Pipelines; Throughput; FPGA; SHA-3; hash algorithm; high performance; pipeline;

fLanguage

English

Publisher

ieee

Conference_Titel

Embedded Computing (MECO), 2015 4th Mediterranean Conference on

Conference_Location

Budva

Print_ISBN

978-1-4799-8999-7

Type

conf

DOI

10.1109/MECO.2015.7181868

Filename

7181868