Evaluation of phosphorous pile-up at the Si/SiO/sub 2/ interface

As we all know from the famous prediction for the micron order transistor era, which Gordon Moore predicted, the performance of transistors improved exponentially, but it doesn´t quite follow his prediction, any more. The performance of transistor is now governed by bland new approaches, for example applying the new materials (high-k, metal gate, strain Si and etc.) and/or non-planar structures, not by the simple device shrinkage. Of those new technologies, SOI-CMOS is one of the best candidates for the next generation CMOS. At the time when SOI-CMOS technology is adopted, however, extensive thinning of the active layer is mandatory. The Si/SiO₂ interface effect obviously becomes significant, since the channel region has greater antenna ratio for peripheral insulator. Up until now, dopant loss at the Si/SiO₂ interface has been studied intensively. Macroscopic understanding of dopant diffusion is well achieved, but none has been reported on sub-100nm Si, where electrical inactivation due to the dopant trapping, Si/SiO₂ interface effect and strain from peripheral dielectric films has significant effects on the electrical properties compare to the one in bulk. The authors hereby discuss the electrical properties of the fabricated nano-Si wire devices to investigate the dopant diffusion by comparing the conductivities of those devices with different thermal histories