Effect of Self-Heating on HCI Lifetime Prediction in SOI Technologies

In this work we have characterized the self-heating in NMOS transistors using gate resistance methodology. The resulting self-heating model was used to estimate the channel temperature during DC HCI stress. Furthermore, the same model (Arrhenius) was used to extrapolate HCI lifetime corresponding to analog and digital applications. And this is demonstrated for NMOS transistor and for PMOS transistor. This is the first investigation of SH impact on HCI DC degradation for both analog and digital applications and the first proposed methodology to correct HCI DC dataset from SH contribution