Temperature Effects on the Hot-Carrier Induced Degradation of pMOSFETs

Author

Chen, Shuang-Yuan ; Tu, Chia-Hao ; Lin, Jung-Chun ; Kao, Po-Wei ; Lin, Wen-Cheng ; Jhou, Ze-Wei ; Chou, Sam ; Ko, Joe ; Haung, Heng-Sheng

Author_Institution

Inst. of Mechatronic Eng., Nat. Taipei Univ. of Technol.

fYear

2006

fDate

Oct. 16 2006-Sept. 19 2006

Firstpage

163

Lastpage

166

Abstract

Low voltages in various stress modes and temperatures were applied on two kinds of pMOSFETs to investigate the hot-carrier (HC) induced degradation. Contrary to conventional concepts, this investigation demonstrates that the worst conditions for pMOSFET HC reliability involves CHC mode and at high temperature. The severity of degradation of pMOSFETs has become comparable to their nMOSFET counterparts. A probable damage mechanism is suggested to involve the generation of interface states by the integration of HC and negative biased temperature effect (NBTI). A new empirical lifetime model is proposed in terms of applied voltages and temperatures

Keywords

MOSFET; hot carriers; interface states; semiconductor device breakdown; semiconductor device reliability; stress effects; MOSFET HC reliability; empirical lifetime model; hot-carrier induced degradation; interface states; negative biased temperature effect; probable damage mechanism; temperature effects; Degradation; Hot carrier effects; Hot carriers; Interface states; Low voltage; MOSFET circuits; Niobium compounds; Stress; Temperature distribution; Titanium compounds;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report, 2006 IEEE International

Conference_Location

South Lake Tahoe, CA

ISSN

1930-8841

Print_ISBN

1-4244-0296-4

Electronic_ISBN

1930-8841

Type

conf

DOI

10.1109/IRWS.2006.305236

Filename

4098713