A 16-bit 1MS/s 44mW successive approximation register analog-to-digital converter achieving signal-to-noise-and-distortion-ratio of 94.3dB

A relatively low-power 16-bit 1MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. Based on the typical structure of SAR ADC, some effective techniques including bootstrapped sampling-switch used to suppress nonlinear distortion, dynamic comparator to reduce power dissipation and the offset-calibration to ensure conversion accuracy have been employed. The off-chip search algorithm is developed against the harmonic distortion resulted from capacitor mismatch. Simulation with parasitism extracted from the layout demonstrates that the ADC achieves signal-to-noise-and-distortion-ratio (SNDR) of 94.3dB at 1MSamples/s, 500KHz input frequency and consumes 44mW from a 1.8V power supply. With the 0.18μm complementary metal-oxide semiconductor (CMOS) process and metal-insulator-metal (MIM) capacitor, the ADC core including decoupling capacitors occupies an active area of 1.0mm×1.4mm.