High voltage silicon-on-insulator (SOI) MOSFETs

Author

Lu, Qin ; Ratnam, P. ; Salama, C. Andre T

Author_Institution

Dept. of Electr. Eng., Toronto Univ., Ont., Canada

fYear

1991

fDate

22-24 Apr 1991

Firstpage

36

Lastpage

39

Abstract

Novel lateral high-voltage SOI MOSFETs capable of withstanding up to 400 V are presented. The design optimization, fabrication, and experimental results obtained for these devices are presented. The devices can be implemented using a CMOS-SOI compatible process. To ensure high voltage capability, the reduced surface field (RESURF) technique and field plates are used. The blocking, DC, and transient characteristics of the devices were investigated both theoretically and experimentally. Optimization of the process parameters involved in the design of the structures is presented

Keywords

insulated gate field effect transistors; power transistors; semiconductor-insulator boundaries; 400 V; CMOS-SOI compatible process; DC characteristics; HV transistors; RESURF; SOI MOSFETs; blocking characteristics; design optimization; fabrication; field plates; high voltage capability; reduced surface field; transient characteristics; CMOS process; CMOS technology; Design optimization; Electric breakdown; Fabrication; Ice; Low voltage; MOSFETs; Silicon on insulator technology; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1991. ISPSD '91., Proceedings of the 3rd International Symposium on

Conference_Location

Baltimore, MD

ISSN

1063-6854

Print_ISBN

0-7803-0009-2

Type

conf

DOI

10.1109/ISPSD.1991.146061

Filename

146061