Reliability of NAND-2 CMOS gates from threshold voltage variations

The high-level approach for estimating circuit reliability tends to consider the probability of failure of a logic gate as a constant, and work towards the higher levels. With scaling, such gate-centric approaches become highly inaccurate, as both transistors and input vectors drastically affect the probability of failure of the logic gates. This paper will present a transistor-level gate failure analysis starting from threshold voltage variations. We will briefly review the state-of-the-art, and rely upon freshly reported results for threshold voltage variations. These will be used to estimate the probabilities of failure of a classical NAND-2 CMOS gate for (a few) different technologies, voltages, and input vectors. They will also reveal huge differences between the highest and the lowest probabilities of failure, and will show how strongly these are affected by the supply voltage.