Optimization of a latched comparator for high-speed analog-to-digital converters

Author

Ockey, Rachelle ; Syrzycki, Marek

Author_Institution

Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada

Volume

1

fYear

1999

fDate

9-12 May 1999

Firstpage

403

Abstract

Reports on the optimization of a latched comparator for use in a high speed analog to digital converter (ADC). Optimization of the comparator was achieved through variations of transistor dimensions and layout designs. Specifically three layout styles, fill-analog style, partial-analog style and digital-like style were created in 0.5 /spl mu/m MOSIS and 0.35 /spl mu/m TSMC CMOS technologies. HSPICE simulation results show definite performance variations for comparators with different transistor dimensions and with different layout styles.

Keywords

CMOS integrated circuits; SPICE; analogue-digital conversion; circuit optimisation; circuit simulation; comparators (circuits); high-speed integrated circuits; integrated circuit layout; 0.35 micron; 0.5 micron; HSPICE simulation results; MOSIS; TSMC CMOS; digital-like style; fill-analog style; high-speed analog-to-digital converters; latched comparator; layout designs; partial-analog style; transistor dimensions; Analog-digital conversion; CMOS technology; Circuits; Design optimization; Latches; Logic; Preamplifiers; Throughput; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1999 IEEE Canadian Conference on

Conference_Location

Edmonton, Alberta, Canada

ISSN

0840-7789

Print_ISBN

0-7803-5579-2

Type

conf

DOI

10.1109/CCECE.1999.807232

Filename

807232