DocumentCode
3479954
Title
Practical Cache Design Techniques For Today´s RISC And CISC CPUS
Author
Handy, Jim
Author_Institution
Integrated Device Technology, Inc.
fYear
1991
fDate
16-18 April 1991
Firstpage
283
Lastpage
288
Abstract
Cache memories are moving into the forefront of popularity. Most microprocessor system designers can now expect to be called upon to design or implement a cache at some time in their carreers. It is somewhat difficult deciding where to start when first confronted with the task of designing a cache from scratch. This paper will focus on techniques which can be used in microprocessor cache designs to improve system throughput. Examples are shown using Intel´s i486 processor, and the P3000 RISC processor.
Keywords
Backplanes; Cache memory; Costs; Microprocessors; Multiprocessing systems; Random access memory; Reduced instruction set computing; System buses; Throughput; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electro International, 1991
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ELECTR.1991.718222
Filename
718222
Link To Document