Power and Variability Improvement of an Asynchronous Router Using Stacking and Dual-Vth Approaches

Below 45nm technology, process variation causes the occurrence of unpredictable characteristics in fabricated transistors. In this paper, a platform has been developed to examine Die-to-Die process and environment variations impacts on power and delay of network-on-chip routers. As a benchmark an asynchronous router will be considered. To reduce power, Power Delay Product (PDP) and variability of this router, three approaches, namely Suitable Sizing, Stacking and Dual-V_th are proposed. By using Suitable Sizing and applying Stacking approaches on input ports of a particular router configuration, power and PDP are reduced by 41.37% and 39.31%, respectively, for 3.63% delay increase only. Simultaneous use of Dual-V_th and Suitable Sizing approaches in one of the router configurations causes the reduction of power and PDP by 27.74% and 26.54%, respectively, for a delay overhead of 1.74%. Our proposed approaches reduce the router variability to some parameters variation such as V_dd, V_th, and PMOS and NMOS transistors length.