Architectural synthesis of timed asynchronous systems

Author

Bachman, Brandon M. ; Zheng, Hao ; Myers, Chris J.

Author_Institution

Comput. Syst. Lab., Hewlett-Packard Co., Cupertino, CA, USA

fYear

1999

fDate

1999

Firstpage

354

Lastpage

363

Abstract

Describes a new method for the architectural synthesis of timed asynchronous systems. Due to the variable delays associated with asynchronous resources, implicit schedules are created by the addition of supplementary constraints between resources. Since the number of schedules grows exponentially with respect to the size of the given data flow graph, pruning techniques are introduced which dramatically improve the run-time without significantly affecting the quality of the results. Using a combination of data and resource constraints, as well as an analysis of bounded delay information, our method determines the minimum number of resources and registers needed to implement a given schedule. Results are demonstrated using some high-level synthesis benchmark circuits and an industrial example

Keywords

asynchronous circuits; data flow graphs; delay circuits; high level synthesis; scheduling; architectural synthesis; asynchronous resources; bounded delay information; data constraints; data flow graph size; high-level synthesis benchmark circuits; implicit schedules; pruning techniques; registers; resource constraints; results quality; run-time; supplementary constraints; timed asynchronous systems; variable delays; Circuits; Delay; Flow graphs; High level synthesis; Information analysis; Job shop scheduling; Registers; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 1999. (ICCD '99) International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-7695-0406-X

Type

conf

DOI

10.1109/ICCD.1999.808566

Filename

808566