DocumentCode
3481843
Title
A Scalable Multiplier for Arbitrary Large Numbers Supporting Homomorphic Encryption
Author
Abozaid, Ghada ; El-Mahdy, Ahmed ; Wada, Yasuhiro
Author_Institution
Comput. Sci. & Eng. Dept., Egypt-Japan Univ. of Sci. & Technol., Alexandria, Egypt
fYear
2013
fDate
4-6 Sept. 2013
Firstpage
969
Lastpage
975
Abstract
With the advent of cloud computing, encrypting remote program execution becomes plausible. Homomorphic encryption scheme is a potentially promising to realize that. However, it is not practically utilized due to its extremely slow execution speed. The scheme generally requires manipulating arbitrary large operand sizes, reaching out to billions of bits. This paper focuses on multiplication, as it is a fundamental operation in homomorphic encryption scheme. The scalability design aspect of multiplication is much more emphasized than in existing multiplier designs, in particular, transferring operands from memory can potentially be a limiting factor. Moreover, the area and speed of the multiplier core has to scale proportionally with the operand sizes. Additionally, the design has to efficiently handle variably sized operands, keeping hardware utilization as high as possible. In this paper, we propose a new regular multiplier design, based on the well-known serial/parallel design that allows for such requirements. It integrates pipelining and parallel operand partitioning to streamline memory transfers. The base design is verified by constructing a VHDL model, and evaluated analytically. The proposed accelerator architecture achieves linear time and cost complexities, and then can realize the linear scalability sought for homomorphic encryption applicability.
Keywords
cloud computing; computational complexity; cryptography; hardware description languages; multiplying circuits; pipeline arithmetic; VHDL model; accelerator architecture; cloud computing; cost complexity; homomorphic encryption scheme; linear scalability; linear time complexity; multiplication; parallel operand partitioning; pipeline integration; remote program execution encryption; scalable multiplier design; serial-parallel design; streamline memory transfer; Adders; Algorithm design and analysis; Bandwidth; Encryption; Hardware; Logic gates; FHE; Large numbers; Multiplier; PSPM; Pipeline; gprof;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital System Design (DSD), 2013 Euromicro Conference on
Conference_Location
Los Alamitos, CA
Type
conf
DOI
10.1109/DSD.2013.110
Filename
6628383
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