Advanced Poly-Si NMIS and Poly-Si/TiN PMIS Hybrid-Gate High-k CMIS using PVD/CVD-Stacked TiN and Local Strain Technique

Author

Nishida, Y. ; Kawahara, T. ; Sakashita, S. ; Mizutani, M. ; Yamanari, S. ; Higashi, M. ; Murata, N. ; Inoue, M. ; Yugami, J. ; Endo, S. ; Hayashi, T. ; Yamashita, T. ; Oda, H. ; Inoue, Y.

Author_Institution

Renesas Technol. Corp., Itami

fYear

2007

fDate

12-14 June 2007

Firstpage

214

Lastpage

215

Abstract

Performance of advanced hybrid-gate CMOS (poly-Si/HfSiON nMIS and poly-Si/TiN/HfSiON pMIS) is demonstrated. V_th of pMIS is controlled by fluorine implantation and by PVD/CVD-stacked TiN, which has higher WF than conventional single-CVD TiN. This combination enables sufficient V_th-control without degradation of device characteristics by excessive fluorine. Performance boosters such as strain enhancement techniques and laser annealing are easily and successfully introduced, and high current drivability is obtained. This advanced hybrid structure is promising for CMIS platforms of 45-nm node and beyond.

Keywords

MIS devices; chemical vapour deposition; elemental semiconductors; laser beam annealing; silicon; NMIS; PMIS hybrid-gate high-k CMIS; PVD/CVD; fluorine implantation; laser annealing; local strain technique; Annealing; Atherosclerosis; Capacitive sensors; Degradation; Fabrication; High K dielectric materials; High-K gate dielectrics; Stress; Surface-mount technology; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-03-1

Type

conf

DOI

10.1109/VLSIT.2007.4339697

Filename

4339697