• DocumentCode
    3485197
  • Title

    Record-high performance 32 nm node pMOSFET with advanced Two-step recessed SiGe-S/D and stress liner technology

  • Author

    Yasutake, N. ; Azuma, A. ; Ishida, T. ; Kusunoki, N. ; Mori, S. ; Itokawa, H. ; Mizushima, I. ; Okamoto, S. ; Morooka, T. ; Aoki, N. ; Kawanaka, S. ; Inaba, S. ; Toyoshima, Y.

  • Author_Institution
    Toshiba Corp. Semicond. Co., Yokohama
  • fYear
    2007
  • fDate
    12-14 June 2007
  • Firstpage
    48
  • Lastpage
    49
  • Abstract
    Two-step recessed SiGe-S/D pMOSFET [1] has been optimized with a combination of compressive stress liner. Optimization on source and drain overlap, defect control and elevated SiGe-S/D structure are discussed experimentally. As a result of the careful optimization, record high drive current of 714 muA/mum at Vdd=1.0 V, Ioff =100 nA/mum at 24 nm gate length, is demonstrated.
  • Keywords
    Ge-Si alloys; power MOSFET; semiconductor device testing; SiGe; compressive stress liner; defect control; pMOSFET; size 32 nm; stress liner technology; two-step recessed technology; Annealing; Boron; Compressive stress; Degradation; Electrodes; Germanium silicon alloys; Implants; MOSFET circuits; Silicon germanium; Stress control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, 2007 IEEE Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-4-900784-03-1
  • Type

    conf

  • DOI
    10.1109/VLSIT.2007.4339722
  • Filename
    4339722
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3485197