DocumentCode
3485404
Title
A new model for the performance evaluation of synchronous circuit switched multistage interconnection networks
Author
Hsiao, Shuo-Hsien ; Chen, C. Y Roger
Author_Institution
Div. of Adv. Workstations & Syst., IBM, Austin, TX, USA
fYear
1993
fDate
13-16 Apr 1993
Firstpage
773
Lastpage
777
Abstract
Patel (1981) proposed a probabilistic approach to analyze the performance of multiprocessor systems using synchronous multistage interconnection networks (MINs) based on a uniform reference model and the assumption of independent requests. Through extensive simulation, the authors have found that, in many cases, their model will result in rather significant inaccuracy. the factors which cause inaccuracy in Patel´s model are investigated in detail. A new queueing model is then proposed and is shown to be very accurate. Since only six states are needed, this new model is very efficient computationally
Keywords
circuit switching; multiprocessing systems; multiprocessor interconnection networks; performance evaluation; queueing theory; independent requests; multiprocessor systems; performance evaluation; queueing model; synchronous circuit switched multistage interconnection networks; uniform reference model; Communication switching; Computer networks; Concurrent computing; Integrated circuit interconnections; Multiprocessing systems; Multiprocessor interconnection networks; Packet switching; Switching circuits; Tail; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing Symposium, 1993., Proceedings of Seventh International
Conference_Location
Newport, CA
Print_ISBN
0-8186-3442-1
Type
conf
DOI
10.1109/IPPS.1993.262783
Filename
262783
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