• DocumentCode
    3486143
  • Title

    Network flow-based power optimization under timing constraints in MSV-driven floorplanning

  • Author

    Ma, Qiang ; Young, Evangeline F Y

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Hong Kong
  • fYear
    2008
  • fDate
    10-13 Nov. 2008
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    Power consumption has become a crucial problem in modern circuit design. Multiple Supply Voltage (MSV) design is introduced to provide higher flexibility in controlling the power and performance trade-off. One important requirement of MSV design is that timing constraints of the circuit must be satisfied after voltage assignment of the cells. In this paper, we will show that the voltage assignment task on a given netlist can be formulated as a convex cost dual network flow problem and can be solved optimally in polynomial time using a cost-scaling algorithm when the delay choices of each module are continuous in the real or integer domain. We can make use of this approach to obtain a feasible voltage assignment solution in the general cases with power consumption approximating the minimum one. Furthermore, we will propose a framework to optimize power consumption and physical layout of a circuit simultaneously during the floorplanning stage, by embedding this cost-scaling solver into a simulated annealing based floorplanner. This is effective in practice due to the short running time of the solver. We compared our approach with the latest work [9] on the same problem, and the experimental results show that, using our framework, significant improvement on power saving (18% less power cost on average) can be achieved in much less running time (7times faster on average) for all the test cases, which confirms the effectiveness of our approach.
  • Keywords
    circuit layout; power consumption; simulated annealing; timing; convex cost dual network flow problem; cost-scaling algorithm; floorplanning stage; multiple supply voltage; network flow-based power optimization; power consumption; power saving; simulated annealing; timing constraints; Circuit simulation; Circuit synthesis; Constraint optimization; Cost function; Delay effects; Energy consumption; Polynomials; Simulated annealing; Timing; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    978-1-4244-2819-9
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2008.4681544
  • Filename
    4681544