• DocumentCode
    348615
  • Title

    Equivalence checking of hierarchical combinational circuits

  • Author

    Williams, Poul Frederick ; Hulgaard, Henrik ; Andersen, H.

  • Author_Institution
    Dept. of Inf. Technol., Tech. Univ., Lyngby, Denmark
  • Volume
    1
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    355
  • Abstract
    This paper presents a method for verifying that two hierarchical combinational circuits implement the same Boolean functions. The key new feature of the method is its ability to exploit the modularity of the circuits to reuse results obtained from one part of the circuits in other parts. We demonstrate the method on large adder and multiplier circuits
  • Keywords
    Boolean functions; adders; binary decision diagrams; circuit analysis computing; combinational circuits; formal verification; logic CAD; multiplying circuits; Boolean functions; OBDD; adder circuits; cut propagation; equivalence checking; hierarchical combinational circuits; multiplier circuits; ordered BDD; Adders; Arithmetic; Boolean functions; Combinational circuits; Data structures; Design automation; Difference equations; Information technology; Integrated circuit interconnections; Manuals;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
  • Conference_Location
    Pafos
  • Print_ISBN
    0-7803-5682-9
  • Type

    conf

  • DOI
    10.1109/ICECS.1999.812296
  • Filename
    812296
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=348615