• DocumentCode
    3486627
  • Title

    On efficient Monte Carlo-based Statistical Static Timing Analysis of digital circuits

  • Author

    Jaffari, Javid ; Anis, Mohab

  • Author_Institution
    Spry Design Autom, Waterloo, ON
  • fYear
    2008
  • fDate
    10-13 Nov. 2008
  • Firstpage
    196
  • Lastpage
    203
  • Abstract
    The Monte-Carlo (MC) technique is a well-known solution for statistical analysis. In contrast to probabilistic (non-Monte Carlo) statistical static timing analysis (SSTA) techniques, which are typically derived from simple statistical or timing models, the MC-based SSTA technique encompasses complicated timing and process variation models. However, a precise analysis that involves a traditional MC-based technique requires many timing simulation runs (1000s). In this paper, the behavior of the critical delay of digital circuits is investigated by using a Legendre polynomial-based ANOVA decomposition. The analysis verifies that the variance of the critical delay is mainly due to the pairwise interactions among the principal components (PCs) of the process parameters. Based on this fact, recent progress on the MC-based SSTA, through Latin hypercube sampling (LHS), is also studied. It is shown that this technique is prone to inefficient critical delay variance and quantile estimating. Inspired by the decomposition observations, an efficient algorithm is proposed which produces optimally low L2-discrepancy quasi-MC (QMC) samples which significantly improve the precision of critical delay statistical estimations, compared with that of the MC, LHS, and traditional QMC techniques.
  • Keywords
    Legendre polynomials; Monte Carlo methods; VLSI; decomposition; digital circuits; principal component analysis; Latin hypercube sampling; Legendre polynomial-based ANOVA decomposition; Monte Carlo-based statistical static timing analysis; critical delay statistical estimation; digital VLSI circuits; principal components; process variation models; timing models; Analysis of variance; Analytical models; Circuit analysis; Circuit simulation; Delay estimation; Digital circuits; Personal communication networks; Polynomials; Statistical analysis; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    978-1-4244-2819-9
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2008.4681574
  • Filename
    4681574