DocumentCode
3487105
Title
Permutation on the mesh with reconfigurable bus: algorithms and practical considerations
Author
Lu, Yen-Wen ; Burr, James B. ; Peterson, Allen M.
Author_Institution
Dept. of Electr. Eng., Stanford Univ., CA, USA
fYear
1993
fDate
13-16 Apr 1993
Firstpage
298
Lastpage
308
Abstract
Permutation is a common problem in both computation and communication. The authors add the buses to the mesh-connected multiprocessors and introduce the tokens to control the buses. They propose to use the mesh with segmented reconfigurable bus to increase performance of data routing. Segmented reconfigurable bus can not only use the bus-token more efficiently than the traditional bus, but also reduce interconnection delay. The authors choose the segment length to balance latency and throughput of the system to get better performance. In the simulation, the mesh with segmented reconfigurable bus can finish N ×N permutation in .6065 N steps in average
Keywords
multiprocessor interconnection networks; reconfigurable architectures; N×N permutation; data routing; interconnection delay; latency; mesh-connected multiprocessors; reconfigurable bus; simulation; throughput; Circuits; Communication system control; Computational modeling; Costs; Delay; Nearest neighbor searches; Parallel processing; Routing; Throughput; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing Symposium, 1993., Proceedings of Seventh International
Conference_Location
Newport, CA
Print_ISBN
0-8186-3442-1
Type
conf
DOI
10.1109/IPPS.1993.262896
Filename
262896
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